diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -52,6 +52,8 @@
 
 #define DEPROGBWPCLIMIT		60
 
+#define PEAK_BW_THRESHOLD	20000
+
 struct intel_psf_gv_point {
 	u8 clk; /* clock in multiples of 16.6666 MHz */
 };
@@ -587,6 +589,33 @@
 	return num_channels * (channel_width / 8) * dclk;
 }
 
+static void xe3_add_peakbw_threshold(struct intel_display *display)
+{
+	u8 qgv_points = display->bw.max[0].num_qgv_points;
+
+	if (!HAS_PEAK_BW_THRESHOLD(display))
+		return;
+
+	if (qgv_points >= I915_NUM_QGV_POINTS) {
+		drm_dbg_kms(display->drm, "QGV points maxed out; skipping peak bandwidth threshold.\n");
+		return;
+	}
+
+	if (qgv_points <= 1)
+		return;
+
+	for (int i = 0; i < ARRAY_SIZE(display->bw.max); i++) {
+		struct intel_bw_info *bi = &display->bw.max[i];
+
+		bi->num_qgv_points++;
+		bi->peakbw[qgv_points] = PEAK_BW_THRESHOLD;
+		bi->deratedbw[qgv_points] = PEAK_BW_THRESHOLD;
+	}
+
+	drm_dbg_kms(display->drm, "An extra QGV point %d added for Peak bw threshod of %d\n",
+		    qgv_points, PEAK_BW_THRESHOLD);
+}
+
 static int tgl_get_bw_info(struct intel_display *display,
 			   const struct dram_info *dram_info,
 			   const struct intel_soc_bw_params *soc_bw_params,
@@ -684,6 +713,9 @@
 		}
 	}
 
+	/* For xe3 cases add an extra qgv point for Peak bw threshold */
+	xe3_add_peakbw_threshold(display);
+
 	/*
 	 * In case if SAGV is disabled in BIOS, we always get 1
 	 * SAGV point, but we can't send PCode commands to restrict it
diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h b/drivers/gpu/drm/i915/display/intel_display_device.h
--- a/drivers/gpu/drm/i915/display/intel_display_device.h
+++ b/drivers/gpu/drm/i915/display/intel_display_device.h
@@ -191,6 +191,7 @@
 #define HAS_MBUS_JOINING(__display)	((__display)->platform.alderlake_p || DISPLAY_VER(__display) >= 14)
 #define HAS_MSO(__display)		(DISPLAY_VER(__display) >= 12)
 #define HAS_OVERLAY(__display)		(DISPLAY_INFO(__display)->has_overlay)
+#define HAS_PEAK_BW_THRESHOLD(__display)	(DISPLAY_VER(__display) >= 30)
 #define HAS_PIPEDMC(__display)		(DISPLAY_VER(__display) >= 12)
 #define HAS_PIXEL_NORMALIZER(__display)	(DISPLAY_VER(__display) >= 35)
 #define HAS_PSR(__display)		(DISPLAY_INFO(__display)->has_psr)