117 lines
4.5 KiB
Diff
117 lines
4.5 KiB
Diff
From: Gaggery Tsai <gaggery.tsai@intel.com>
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Date: Thu, 17 Apr 2026 10:30:00 -0700
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Subject: [PATCH] drm/i915/psr: exit Panel Replay during updates to work around ALPM lag
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Panel Replay ALPM AUX-Less wake/sleep cycling cannot resume selective
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updates at frame rate on the LGD OLED panel in the Dell XPS 14
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DA14260. The panel's internal timing engine appears to need a
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per-frame timing beacon to resume quickly after ALPM sleep; without
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it, the source commits at 120 Hz but visible frames land around
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15 Hz.
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Work around by temporarily exiting Panel Replay in
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frontbuffer_flush() before each frame update. Re-entry into PR (with
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ALPM) is deferred by 50 ms via dc3co_work so that during continuous
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motion the link stays on (cursor/video smooth), and PR re-engages
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after 50 ms of no further updates (idle power savings preserved).
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The delay was chosen empirically:
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| Delay | Idle (10x avg) | Cursor motion (3x avg) |
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|--------|----------------|------------------------|
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| 50 ms | 3268 mW | 8749 mW |
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| 100 ms | 3436 mW | 9088 mW |
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| 200 ms | 3484 mW | 9104 mW |
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| stock | 3384 mW | ~15 Hz visible lag |
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| PSR2 | 4060 mW | 9191 mW |
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50 ms gives the best idle and cursor-motion power while remaining
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subjectively identical in smoothness to longer delays.
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Repurpose the existing dc3co_work delayed_work as the re-entry timer:
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each frontbuffer_flush cancels+rearms it to 50 ms, and the work
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handler calls intel_psr_activate() when it fires.
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Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com>
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---
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drivers/gpu/drm/i915/display/intel_frontbuffer.c | 1 +
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drivers/gpu/drm/i915/display/intel_psr.c | 33 ++++++++++++++++++
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drivers/gpu/drm/i915/display/intel_psr.h | 1 +
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3 files changed, 35 insertions(+)
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--- a/drivers/gpu/drm/i915/display/intel_frontbuffer.c
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+++ b/drivers/gpu/drm/i915/display/intel_frontbuffer.c
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@@ -97,6 +97,7 @@ static void frontbuffer_flush(struct intel_display *display,
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might_sleep();
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intel_td_flush(display);
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intel_drrs_flush(display, frontbuffer_bits);
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+ intel_psr_panel_replay_exit(display);
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intel_psr_flush(display, frontbuffer_bits, origin);
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intel_fbc_flush(display, frontbuffer_bits, origin);
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}
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--- a/drivers/gpu/drm/i915/display/intel_psr.h
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+++ b/drivers/gpu/drm/i915/display/intel_psr.h
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@@ -40,6 +40,7 @@ int intel_psr_debug_set(struct intel_dp *intel_dp, u64 value);
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void intel_psr_invalidate(struct intel_display *display,
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unsigned frontbuffer_bits,
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enum fb_op_origin origin);
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+void intel_psr_panel_replay_exit(struct intel_display *display);
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void intel_psr_flush(struct intel_display *display,
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unsigned frontbuffer_bits,
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enum fb_op_origin origin);
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--- a/drivers/gpu/drm/i915/display/intel_psr.c
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+++ b/drivers/gpu/drm/i915/display/intel_psr.c
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@@ -1189,6 +1189,8 @@ static void tgl_psr2_disable_dc3co(struct intel_dp *intel_dp)
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intel_display_power_set_target_dc_state(display, DC_STATE_EN_UPTO_DC6);
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psr2_program_idle_frames(intel_dp, psr_compute_idle_frames(intel_dp));
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}
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+
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+static void intel_psr_activate(struct intel_dp *intel_dp);
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static void tgl_dc3co_disable_work(struct work_struct *work)
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{
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@@ -1203,6 +1205,13 @@ static void tgl_dc3co_disable_work(struct work_struct *work)
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if (delayed_work_pending(&intel_dp->psr.dc3co_work))
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goto unlock;
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+ /* Panel Replay ALPM cursor-lag workaround re-activation path. */
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+ if (intel_dp->psr.panel_replay_enabled &&
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+ intel_dp->psr.enabled && !intel_dp->psr.active) {
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+ intel_psr_activate(intel_dp);
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+ goto unlock;
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+ }
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+
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tgl_psr2_disable_dc3co(intel_dp);
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unlock:
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mutex_unlock(&intel_dp->psr.lock);
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@@ -4615,2 +4624,29 @@ int intel_psr_min_guardband(struct intel_crtc_state *crtc_state)
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return psr_min_guardband;
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}
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+
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+/*
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+ * intel_psr_panel_replay_exit - exit Panel Replay during frontbuffer activity
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+ *
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+ * Exits PR on frontbuffer flush and arms dc3co_work with a 50 ms
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+ * delay. Each subsequent flush cancels and rearms the timer. When it
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+ * finally fires, tgl_dc3co_disable_work re-activates PR.
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+ */
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+void intel_psr_panel_replay_exit(struct intel_display *display)
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+{
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+ struct intel_encoder *encoder;
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+
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+ for_each_intel_encoder_with_psr(display->drm, encoder) {
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+ struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
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+
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+ mutex_lock(&intel_dp->psr.lock);
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+ if (intel_dp->psr.panel_replay_enabled &&
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+ intel_dp->psr.sel_update_enabled) {
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+ if (intel_dp->psr.active)
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+ intel_psr_exit(intel_dp);
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+ mod_delayed_work(display->wq.unordered,
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+ &intel_dp->psr.dc3co_work,
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+ msecs_to_jiffies(50));
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+ }
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+ mutex_unlock(&intel_dp->psr.lock);
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+ }
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+}
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