35 lines
1.3 KiB
Diff
35 lines
1.3 KiB
Diff
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
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From: Gaggery Tsai <gaggery.tsai@intel.com>
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Date: Tue, 8 Apr 2026 15:00:00 -0700
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Subject: [PATCH] drm/i915/psr: Allow PSR with VRR on Panther Lake
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The blanket VRR rejection in _psr_compute_config() prevents PSR2
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from coexisting with VRR on all platforms. On Panther Lake (PTL,
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DISPLAY_VER 30), PSR2 + VRR has been tested and works correctly.
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The existing Wa_16011303918 in intel_psr2_config_valid() already
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handles the Alderlake-P stepping-specific VRR incompatibility.
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Remove the blanket check to allow PSR2 + VRR on platforms where
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no specific workaround applies.
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Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com>
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---
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diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
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index 197c238..242077f 100644
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--- a/drivers/gpu/drm/i915/display/intel_psr.c
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+++ b/drivers/gpu/drm/i915/display/intel_psr.c
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@@ -1714,12 +1714,6 @@ static bool _psr_compute_config(struct intel_dp *intel_dp,
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if (!CAN_PSR(intel_dp) || !display->params.enable_psr)
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return false;
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- /*
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- * Currently PSR doesn't work reliably with VRR enabled.
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- */
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- if (crtc_state->vrr.enable)
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- return false;
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-
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entry_setup_frames = intel_psr_entry_setup_frames(intel_dp, conn_state, adjusted_mode);
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if (entry_setup_frames >= 0) {
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