197 lines
7.1 KiB
Diff
197 lines
7.1 KiB
Diff
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
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index c21e0c0ef0b1..e62788328bfd 100644
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--- a/drivers/gpu/drm/i915/display/intel_display_types.h
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+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
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@@ -1780,6 +1780,7 @@ struct intel_psr {
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u32 dc3co_exitline;
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u32 dc3co_exit_delay;
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struct delayed_work dc3co_work;
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+ struct delayed_work panel_replay_reenable_work;
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u8 entry_setup_frames;
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u8 io_wake_lines;
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diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
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index beaa1d62613d..644ab9b1bee9 100644
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--- a/drivers/gpu/drm/i915/display/intel_psr.c
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+++ b/drivers/gpu/drm/i915/display/intel_psr.c
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@@ -2475,6 +2475,7 @@ void intel_psr_disable(struct intel_dp *intel_dp,
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mutex_unlock(&intel_dp->psr.lock);
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cancel_work_sync(&intel_dp->psr.work);
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cancel_delayed_work_sync(&intel_dp->psr.dc3co_work);
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+ cancel_delayed_work_sync(&intel_dp->psr.panel_replay_reenable_work);
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}
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/**
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@@ -2506,6 +2507,7 @@ void intel_psr_pause(struct intel_dp *intel_dp)
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cancel_work_sync(&psr->work);
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cancel_delayed_work_sync(&psr->dc3co_work);
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+ cancel_delayed_work_sync(&psr->panel_replay_reenable_work);
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}
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/**
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@@ -3539,6 +3541,17 @@ static void intel_psr_handle_irq(struct intel_dp *intel_dp)
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drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, DP_SET_POWER_D0);
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}
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+#define PANEL_REPLAY_REENABLE_DELAY_MS 50
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+
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+static bool panel_replay_alpm_cursor_lag_workaround_enabled(struct intel_dp *intel_dp)
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+{
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+ return intel_dp_is_edp(intel_dp) &&
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+ intel_dp->psr.panel_replay_enabled &&
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+ intel_dp->psr.sel_update_enabled &&
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+ intel_has_dpcd_quirk(intel_dp,
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+ QUIRK_PANEL_REPLAY_ALPM_CURSOR_LAG);
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+}
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+
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static void intel_psr_work(struct work_struct *work)
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{
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struct intel_dp *intel_dp =
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@@ -3557,6 +3570,11 @@ static void intel_psr_work(struct work_struct *work)
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if (intel_dp->psr.pause_counter)
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goto unlock;
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+ /* The dedicated delayed work owns re-entry while the workaround is armed. */
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+ if (panel_replay_alpm_cursor_lag_workaround_enabled(intel_dp) &&
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+ delayed_work_pending(&intel_dp->psr.panel_replay_reenable_work))
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+ goto unlock;
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+
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/*
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* We have to make sure PSR is ready for re-enable
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* otherwise it keeps disabled until next full enable/disable cycle.
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@@ -3566,6 +3584,10 @@ static void intel_psr_work(struct work_struct *work)
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if (!__psr_wait_for_idle_locked(intel_dp))
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goto unlock;
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+ if (panel_replay_alpm_cursor_lag_workaround_enabled(intel_dp) &&
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+ delayed_work_pending(&intel_dp->psr.panel_replay_reenable_work))
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+ goto unlock;
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+
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/*
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* The delayed work can race with an invalidate hence we need to
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* recheck. Since psr_flush first clears this and then reschedules we
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@@ -3579,6 +3601,33 @@ static void intel_psr_work(struct work_struct *work)
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mutex_unlock(&intel_dp->psr.lock);
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}
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+static void panel_replay_reenable_work(struct work_struct *work)
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+{
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+ struct intel_dp *intel_dp =
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+ container_of(work, typeof(*intel_dp),
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+ psr.panel_replay_reenable_work.work);
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+
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+ mutex_lock(&intel_dp->psr.lock);
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+
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+ if (!intel_dp->psr.enabled ||
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+ !panel_replay_alpm_cursor_lag_workaround_enabled(intel_dp) ||
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+ intel_dp->psr.pause_counter ||
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+ READ_ONCE(intel_dp->psr.irq_aux_error))
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+ goto unlock;
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+
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+ if (!__psr_wait_for_idle_locked(intel_dp))
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+ goto unlock;
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+
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+ /* Recheck for activity or a newer deadline after the unlocked wait. */
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+ if (delayed_work_pending(&intel_dp->psr.panel_replay_reenable_work) ||
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+ intel_dp->psr.busy_frontbuffer_bits || intel_dp->psr.active)
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+ goto unlock;
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+
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+ intel_psr_activate(intel_dp);
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+unlock:
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+ mutex_unlock(&intel_dp->psr.lock);
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+}
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+
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static void intel_psr_configure_full_frame_update(struct intel_dp *intel_dp)
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{
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struct intel_display *display = to_intel_display(intel_dp);
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@@ -3650,8 +3699,11 @@ void intel_psr_invalidate(struct intel_display *display,
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INTEL_FRONTBUFFER_ALL_MASK(intel_dp->psr.pipe);
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intel_dp->psr.busy_frontbuffer_bits |= pipe_frontbuffer_bits;
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- if (pipe_frontbuffer_bits)
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+ if (pipe_frontbuffer_bits) {
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+ if (panel_replay_alpm_cursor_lag_workaround_enabled(intel_dp))
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+ cancel_delayed_work(&intel_dp->psr.panel_replay_reenable_work);
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_psr_invalidate_handle(intel_dp);
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+ }
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mutex_unlock(&intel_dp->psr.lock);
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}
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@@ -3767,6 +3819,15 @@ void intel_psr_flush(struct intel_display *display,
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if (intel_dp->psr.pause_counter)
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goto unlock;
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+ if (pipe_frontbuffer_bits &&
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+ panel_replay_alpm_cursor_lag_workaround_enabled(intel_dp)) {
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+ intel_psr_exit(intel_dp);
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+ mod_delayed_work(display->wq.unordered,
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+ &intel_dp->psr.panel_replay_reenable_work,
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+ msecs_to_jiffies(PANEL_REPLAY_REENABLE_DELAY_MS));
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+ goto unlock;
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+ }
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+
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if (origin == ORIGIN_FLIP ||
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(origin == ORIGIN_CURSOR_UPDATE &&
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!intel_dp->psr.psr2_sel_fetch_enabled)) {
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@@ -3830,6 +3891,8 @@ void intel_psr_init(struct intel_dp *intel_dp)
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INIT_WORK(&intel_dp->psr.work, intel_psr_work);
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INIT_DELAYED_WORK(&intel_dp->psr.dc3co_work, tgl_dc3co_disable_work);
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+ INIT_DELAYED_WORK(&intel_dp->psr.panel_replay_reenable_work,
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+ panel_replay_reenable_work);
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mutex_init(&intel_dp->psr.lock);
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}
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diff --git a/drivers/gpu/drm/i915/display/intel_quirks.c b/drivers/gpu/drm/i915/display/intel_quirks.c
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index 33245f44c0d5..dc6576016400 100644
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--- a/drivers/gpu/drm/i915/display/intel_quirks.c
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+++ b/drivers/gpu/drm/i915/display/intel_quirks.c
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@@ -86,12 +86,13 @@ static void quirk_edp_limit_rate_hbr2(struct intel_display *display)
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drm_info(display->drm, "Applying eDP Limit rate to HBR2 quirk\n");
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}
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-static void quirk_disable_edp_panel_replay(struct intel_dp *intel_dp)
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+static void quirk_panel_replay_alpm_cursor_lag(struct intel_dp *intel_dp)
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{
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struct intel_display *display = to_intel_display(intel_dp);
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- intel_set_dpcd_quirk(intel_dp, QUIRK_DISABLE_EDP_PANEL_REPLAY);
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- drm_info(display->drm, "Applying disable Panel Replay quirk\n");
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+ intel_set_dpcd_quirk(intel_dp, QUIRK_PANEL_REPLAY_ALPM_CURSOR_LAG);
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+ drm_info(display->drm,
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+ "Applying Panel Replay ALPM cursor lag workaround\n");
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}
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static void quirk_disable_psr2(struct intel_display *display)
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@@ -276,7 +277,7 @@ static const struct intel_dpcd_quirk intel_dpcd_quirks[] = {
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.subsystem_vendor = 0x1028,
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.subsystem_device = 0x0db9,
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.sink_oui = SINK_OUI(0x00, 0x22, 0xb9),
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- .hook = quirk_disable_edp_panel_replay,
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+ .hook = quirk_panel_replay_alpm_cursor_lag,
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},
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/* Dell XPS 16 DA16260 */
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{
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@@ -284,7 +285,7 @@ static const struct intel_dpcd_quirk intel_dpcd_quirks[] = {
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.subsystem_vendor = 0x1028,
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.subsystem_device = 0x0dba,
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.sink_oui = SINK_OUI(0x00, 0x22, 0xb9),
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- .hook = quirk_disable_edp_panel_replay,
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+ .hook = quirk_panel_replay_alpm_cursor_lag,
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},
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};
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diff --git a/drivers/gpu/drm/i915/display/intel_quirks.h b/drivers/gpu/drm/i915/display/intel_quirks.h
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index 970a4fe52faf..50ef333b87a9 100644
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--- a/drivers/gpu/drm/i915/display/intel_quirks.h
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+++ b/drivers/gpu/drm/i915/display/intel_quirks.h
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@@ -23,6 +23,7 @@ enum intel_quirk_id {
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QUIRK_EDP_LIMIT_RATE_HBR2,
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QUIRK_DISABLE_EDP_PANEL_REPLAY,
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QUIRK_DISABLE_PSR2,
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+ QUIRK_PANEL_REPLAY_ALPM_CURSOR_LAG,
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};
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void intel_init_quirks(struct intel_display *display);
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