68 lines
2.3 KiB
Diff
68 lines
2.3 KiB
Diff
diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
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--- a/drivers/gpu/drm/i915/display/intel_bw.c
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+++ b/drivers/gpu/drm/i915/display/intel_bw.c
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@@ -52,6 +52,8 @@
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#define DEPROGBWPCLIMIT 60
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+#define PEAK_BW_THRESHOLD 20000
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+
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struct intel_psf_gv_point {
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u8 clk; /* clock in multiples of 16.6666 MHz */
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};
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@@ -587,6 +589,33 @@
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return num_channels * (channel_width / 8) * dclk;
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}
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+static void xe3_add_peakbw_threshold(struct intel_display *display)
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+{
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+ u8 qgv_points = display->bw.max[0].num_qgv_points;
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+
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+ if (!HAS_PEAK_BW_THRESHOLD(display))
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+ return;
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+
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+ if (qgv_points >= I915_NUM_QGV_POINTS) {
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+ drm_dbg_kms(display->drm, "QGV points maxed out; skipping peak bandwidth threshold.\n");
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+ return;
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+ }
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+
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+ if (qgv_points <= 1)
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+ return;
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+
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+ for (int i = 0; i < ARRAY_SIZE(display->bw.max); i++) {
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+ struct intel_bw_info *bi = &display->bw.max[i];
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+
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+ bi->num_qgv_points++;
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+ bi->peakbw[qgv_points] = PEAK_BW_THRESHOLD;
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+ bi->deratedbw[qgv_points] = PEAK_BW_THRESHOLD;
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+ }
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+
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+ drm_dbg_kms(display->drm, "An extra QGV point %d added for Peak bw threshod of %d\n",
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+ qgv_points, PEAK_BW_THRESHOLD);
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+}
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+
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static int tgl_get_bw_info(struct intel_display *display,
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const struct dram_info *dram_info,
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const struct intel_soc_bw_params *soc_bw_params,
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@@ -684,6 +713,9 @@
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}
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}
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+ /* For xe3 cases add an extra qgv point for Peak bw threshold */
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+ xe3_add_peakbw_threshold(display);
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+
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/*
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* In case if SAGV is disabled in BIOS, we always get 1
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* SAGV point, but we can't send PCode commands to restrict it
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diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h b/drivers/gpu/drm/i915/display/intel_display_device.h
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--- a/drivers/gpu/drm/i915/display/intel_display_device.h
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+++ b/drivers/gpu/drm/i915/display/intel_display_device.h
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@@ -191,6 +191,7 @@
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#define HAS_MBUS_JOINING(__display) ((__display)->platform.alderlake_p || DISPLAY_VER(__display) >= 14)
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#define HAS_MSO(__display) (DISPLAY_VER(__display) >= 12)
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#define HAS_OVERLAY(__display) (DISPLAY_INFO(__display)->has_overlay)
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+#define HAS_PEAK_BW_THRESHOLD(__display) (DISPLAY_VER(__display) >= 30)
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#define HAS_PIPEDMC(__display) (DISPLAY_VER(__display) >= 12)
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#define HAS_PIXEL_NORMALIZER(__display) (DISPLAY_VER(__display) >= 35)
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#define HAS_PSR(__display) (DISPLAY_INFO(__display)->has_psr)
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