Add small AMD Zen 5 TLB sizes display fix to base and BORE kernels

Signed-off-by: Krzysztof Wilczyński <kwilczynski@omarchy.org>

pkgbuilds/linux-omarchy-bore/0220-x86-amd-zen5-tlb-sizes.patch

@@ -0,0 +1,95 @@
+diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
+--- a/arch/x86/include/asm/cpufeatures.h
++++ b/arch/x86/include/asm/cpufeatures.h
+@@ -471,6 +471,8 @@
+ #define X86_FEATURE_AUTOIBRS		(20*32+ 8) /* Automatic IBRS */
+ #define X86_FEATURE_NO_SMM_CTL_MSR	(20*32+ 9) /* SMM_CTL MSR is not present */
+ 
++#define X86_FEATURE_L2_TLB_SIZE_X32	(20*32+14) /* L2 TLB sizes are encoded as multiples of 32 */
++
+ #define X86_FEATURE_GP_ON_USER_CPUID	(20*32+17) /* User CPUID faulting */
+ 
+ #define X86_FEATURE_PREFETCHI		(20*32+20) /* Prefetch Data/Instruction to Cache Level */
+diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
+--- a/arch/x86/kernel/cpu/amd.c
++++ b/arch/x86/kernel/cpu/amd.c
+@@ -1190,7 +1190,7 @@ static unsigned int amd_size_cache(struct cpuinfo_x86 *c, unsigned int size)
+ 
+ static void cpu_detect_tlb_amd(struct cpuinfo_x86 *c)
+ {
+-	u32 ebx, eax, ecx, edx;
++	u32 ebx, eax, ecx, edx, shift, tmp;
+ 	u16 mask = 0xfff;
+ 
+ 	if (c->x86 < 0xf)
+@@ -1199,10 +1199,12 @@ static void cpu_detect_tlb_amd(struct cpuinfo_x86 *c)
+ 	if (c->extended_cpuid_level < 0x80000006)
+ 		return;
+ 
++	shift = !!cpu_has(c, X86_FEATURE_L2_TLB_SIZE_X32) * 5;
++
+ 	cpuid(0x80000006, &eax, &ebx, &ecx, &edx);
+ 
+-	tlb_lld_4k = (ebx >> 16) & mask;
+-	tlb_lli_4k = ebx & mask;
++	tlb_lld_4k = ((ebx >> 16) & mask) << shift;
++	tlb_lli_4k = (ebx & mask) << shift;
+ 
+ 	/*
+ 	 * K8 doesn't have 2M/4M entries in the L2 TLB so read out the L1 TLB
+@@ -1214,16 +1216,18 @@ static void cpu_detect_tlb_amd(struct cpuinfo_x86 *c)
+ 	}
+ 
+ 	/* Handle DTLB 2M and 4M sizes, fall back to L1 if L2 is disabled */
+-	if (!((eax >> 16) & mask))
++	tmp = ((eax >> 16) & mask) << shift;
++	if (!tmp)
+ 		tlb_lld_2m = (cpuid_eax(0x80000005) >> 16) & 0xff;
+ 	else
+-		tlb_lld_2m = (eax >> 16) & mask;
++		tlb_lld_2m = tmp;
+ 
+ 	/* a 4M entry uses two 2M entries */
+ 	tlb_lld_4m = tlb_lld_2m >> 1;
+ 
+ 	/* Handle ITLB 2M and 4M sizes, fall back to L1 if L2 is disabled */
+-	if (!(eax & mask)) {
++	tmp = (eax & mask) << shift;
++	if (!tmp) {
+ 		/* Erratum 658 */
+ 		if (c->x86 == 0x15 && c->x86_model <= 0x1f) {
+ 			tlb_lli_2m = 1024;
+@@ -1231,8 +1235,9 @@ static void cpu_detect_tlb_amd(struct cpuinfo_x86 *c)
+ 			cpuid(0x80000005, &eax, &ebx, &ecx, &edx);
+ 			tlb_lli_2m = eax & 0xff;
+ 		}
+-	} else
+-		tlb_lli_2m = eax & mask;
++	} else {
++		tlb_lli_2m = tmp;
++	}
+ 
+ 	tlb_lli_4m = tlb_lli_2m >> 1;
+ 
+diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
+--- a/arch/x86/kernel/cpu/common.c
++++ b/arch/x86/kernel/cpu/common.c
+@@ -857,7 +857,7 @@ static void get_model_name(struct cpuinfo_x86 *c)
+ 
+ void cpu_detect_cache_sizes(struct cpuinfo_x86 *c)
+ {
+-	unsigned int n, dummy, ebx, ecx, edx, l2size;
++	unsigned int n, dummy, ebx, ecx, edx, l2size, shift __maybe_unused;
+ 
+ 	n = c->extended_cpuid_level;
+ 
+@@ -877,7 +877,9 @@ void cpu_detect_cache_sizes(struct cpuinfo_x86 *c)
+ 	l2size = ecx >> 16;
+ 
+ #ifdef CONFIG_X86_64
++	shift = !!cpu_has(c, X86_FEATURE_L2_TLB_SIZE_X32) * 5;
+ 	c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff);
++	c->x86_tlbsize <<= shift;
+ #else
+ 	/* do processor-specific cache resizing */
+ 	if (this_cpu->legacy_cache_size)

pkgbuilds/linux-omarchy-bore/PKGBUILD

@@ -65,6 +65,7 @@ source=(
   0210-pstate.patch{,.sig}
   0211-amd-pstate-fixes.patch{,.sig}
   0212-amd-pstate-epp-cache.patch{,.sig}
+  0220-x86-amd-zen5-tlb-sizes.patch{,.sig}
   0250-zsmalloc.patch{,.sig}
   0260-mglru-exec-protect.patch{,.sig}
   0270-ksm-rmap-walk.patch{,.sig}
@@ -185,6 +186,8 @@ b2sums=('48551bee71cd02815136fb8abe7da4464c2e17c89ef35cb0c0530c8b969fe12127ca97a
         'SKIP'
         '2f24f88d8f960148046c36222fdaaadfed2ca88c60240fa1d111430898192ca45aeaa93a3afa24ad02b11c4dc8c3904a92f17c0284396f2f43352ad934a35056'
         'SKIP'
+        'e59c4da548b2ea4fd6144886e3e2e765b3e73972121e9e73dbc05c066834b2b35e6ef4c17617e77efc90260566bf7c0910d2138d8d5c1c3b6094eeac9de64cfe'
+        'SKIP'
         '9809e258eb684b80d508fa2f2fa270683b62bd1412ed05a970114aaa7d84c37c0beaea51f9ff8c6ee1bc7318c4aee3725e9a1131fefb51ba700801de6ac414c5'
         'SKIP'
         'f115e8c80d723f7c24e6b1638b801cd664bef20acb1d2f6e6f5612744b916278693011782228cd3f4d0518654b8d53309bc5b06bbe8ed722fab9995f369bf548'
@@ -378,6 +381,8 @@ sha256sums=('55ddf0df8325d9dad96fcff7bd93977d22e3f50af06527572af59b77c7632b78'
             'SKIP'
             '66eb2c49dbf708cc781d411d0e44ed613480f0ef66d522272929d9cb7bb21e93'
             'SKIP'
+            '718b40e15350049e03c0ed281b9257fca5432b8dec2e0e145e8b26507ee8892d'
+            'SKIP'
             'b7ba949eea77e169aceb2c401d4eb83a7413aab6f15ee2a7ab1a96352f0aa12d'
             'SKIP'
             '341424b925d506869793686e22ea8f095a34048595ebebec409c0a7bbd346ca2'

pkgbuilds/linux-omarchy/0220-x86-amd-zen5-tlb-sizes.patch

@@ -0,0 +1,95 @@
+diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
+--- a/arch/x86/include/asm/cpufeatures.h
++++ b/arch/x86/include/asm/cpufeatures.h
+@@ -471,6 +471,8 @@
+ #define X86_FEATURE_AUTOIBRS		(20*32+ 8) /* Automatic IBRS */
+ #define X86_FEATURE_NO_SMM_CTL_MSR	(20*32+ 9) /* SMM_CTL MSR is not present */
+ 
++#define X86_FEATURE_L2_TLB_SIZE_X32	(20*32+14) /* L2 TLB sizes are encoded as multiples of 32 */
++
+ #define X86_FEATURE_GP_ON_USER_CPUID	(20*32+17) /* User CPUID faulting */
+ 
+ #define X86_FEATURE_PREFETCHI		(20*32+20) /* Prefetch Data/Instruction to Cache Level */
+diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
+--- a/arch/x86/kernel/cpu/amd.c
++++ b/arch/x86/kernel/cpu/amd.c
+@@ -1190,7 +1190,7 @@ static unsigned int amd_size_cache(struct cpuinfo_x86 *c, unsigned int size)
+ 
+ static void cpu_detect_tlb_amd(struct cpuinfo_x86 *c)
+ {
+-	u32 ebx, eax, ecx, edx;
++	u32 ebx, eax, ecx, edx, shift, tmp;
+ 	u16 mask = 0xfff;
+ 
+ 	if (c->x86 < 0xf)
+@@ -1199,10 +1199,12 @@ static void cpu_detect_tlb_amd(struct cpuinfo_x86 *c)
+ 	if (c->extended_cpuid_level < 0x80000006)
+ 		return;
+ 
++	shift = !!cpu_has(c, X86_FEATURE_L2_TLB_SIZE_X32) * 5;
++
+ 	cpuid(0x80000006, &eax, &ebx, &ecx, &edx);
+ 
+-	tlb_lld_4k = (ebx >> 16) & mask;
+-	tlb_lli_4k = ebx & mask;
++	tlb_lld_4k = ((ebx >> 16) & mask) << shift;
++	tlb_lli_4k = (ebx & mask) << shift;
+ 
+ 	/*
+ 	 * K8 doesn't have 2M/4M entries in the L2 TLB so read out the L1 TLB
+@@ -1214,16 +1216,18 @@ static void cpu_detect_tlb_amd(struct cpuinfo_x86 *c)
+ 	}
+ 
+ 	/* Handle DTLB 2M and 4M sizes, fall back to L1 if L2 is disabled */
+-	if (!((eax >> 16) & mask))
++	tmp = ((eax >> 16) & mask) << shift;
++	if (!tmp)
+ 		tlb_lld_2m = (cpuid_eax(0x80000005) >> 16) & 0xff;
+ 	else
+-		tlb_lld_2m = (eax >> 16) & mask;
++		tlb_lld_2m = tmp;
+ 
+ 	/* a 4M entry uses two 2M entries */
+ 	tlb_lld_4m = tlb_lld_2m >> 1;
+ 
+ 	/* Handle ITLB 2M and 4M sizes, fall back to L1 if L2 is disabled */
+-	if (!(eax & mask)) {
++	tmp = (eax & mask) << shift;
++	if (!tmp) {
+ 		/* Erratum 658 */
+ 		if (c->x86 == 0x15 && c->x86_model <= 0x1f) {
+ 			tlb_lli_2m = 1024;
+@@ -1231,8 +1235,9 @@ static void cpu_detect_tlb_amd(struct cpuinfo_x86 *c)
+ 			cpuid(0x80000005, &eax, &ebx, &ecx, &edx);
+ 			tlb_lli_2m = eax & 0xff;
+ 		}
+-	} else
+-		tlb_lli_2m = eax & mask;
++	} else {
++		tlb_lli_2m = tmp;
++	}
+ 
+ 	tlb_lli_4m = tlb_lli_2m >> 1;
+ 
+diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
+--- a/arch/x86/kernel/cpu/common.c
++++ b/arch/x86/kernel/cpu/common.c
+@@ -857,7 +857,7 @@ static void get_model_name(struct cpuinfo_x86 *c)
+ 
+ void cpu_detect_cache_sizes(struct cpuinfo_x86 *c)
+ {
+-	unsigned int n, dummy, ebx, ecx, edx, l2size;
++	unsigned int n, dummy, ebx, ecx, edx, l2size, shift __maybe_unused;
+ 
+ 	n = c->extended_cpuid_level;
+ 
+@@ -877,7 +877,9 @@ void cpu_detect_cache_sizes(struct cpuinfo_x86 *c)
+ 	l2size = ecx >> 16;
+ 
+ #ifdef CONFIG_X86_64
++	shift = !!cpu_has(c, X86_FEATURE_L2_TLB_SIZE_X32) * 5;
+ 	c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff);
++	c->x86_tlbsize <<= shift;
+ #else
+ 	/* do processor-specific cache resizing */
+ 	if (this_cpu->legacy_cache_size)

pkgbuilds/linux-omarchy/PKGBUILD

@@ -64,6 +64,7 @@ source=(
   0210-pstate.patch{,.sig}
   0211-amd-pstate-fixes.patch{,.sig}
   0212-amd-pstate-epp-cache.patch{,.sig}
+  0220-x86-amd-zen5-tlb-sizes.patch{,.sig}
   0250-zsmalloc.patch{,.sig}
   0260-mglru-exec-protect.patch{,.sig}
   0270-ksm-rmap-walk.patch{,.sig}
@@ -182,6 +183,8 @@ b2sums=('48551bee71cd02815136fb8abe7da4464c2e17c89ef35cb0c0530c8b969fe12127ca97a
         'SKIP'
         '2f24f88d8f960148046c36222fdaaadfed2ca88c60240fa1d111430898192ca45aeaa93a3afa24ad02b11c4dc8c3904a92f17c0284396f2f43352ad934a35056'
         'SKIP'
+        'e59c4da548b2ea4fd6144886e3e2e765b3e73972121e9e73dbc05c066834b2b35e6ef4c17617e77efc90260566bf7c0910d2138d8d5c1c3b6094eeac9de64cfe'
+        'SKIP'
         '9809e258eb684b80d508fa2f2fa270683b62bd1412ed05a970114aaa7d84c37c0beaea51f9ff8c6ee1bc7318c4aee3725e9a1131fefb51ba700801de6ac414c5'
         'SKIP'
         'f115e8c80d723f7c24e6b1638b801cd664bef20acb1d2f6e6f5612744b916278693011782228cd3f4d0518654b8d53309bc5b06bbe8ed722fab9995f369bf548'
@@ -373,6 +376,8 @@ sha256sums=('55ddf0df8325d9dad96fcff7bd93977d22e3f50af06527572af59b77c7632b78'
             'SKIP'
             '66eb2c49dbf708cc781d411d0e44ed613480f0ef66d522272929d9cb7bb21e93'
             'SKIP'
+            '718b40e15350049e03c0ed281b9257fca5432b8dec2e0e145e8b26507ee8892d'
+            'SKIP'
             'b7ba949eea77e169aceb2c401d4eb83a7413aab6f15ee2a7ab1a96352f0aa12d'
             'SKIP'
             '341424b925d506869793686e22ea8f095a34048595ebebec409c0a7bbd346ca2'